This application claims the priority of Korean patent application Serial No. 2000-42377 filed on Jul. 24, 2000.
Semiconductor package and method of fabricating the same
The present invention relates to a semiconductor package, and more particularly to a semiconductor package which is minimized and thinned while having reliability and a method of fabricating the same.
As is well known, microelectronic devices have a tendency to be minimized and thinned with its functional development and a semiconductor package mounted on a mother board is also following the tendency in order to realize a mounting of high integration.
Most of these semiconductor packages have a structure that the semiconductor chips are sealed with a sealing material such as Epoxy Molding Compound (EMC) and a plurality of leads are fetched/formed outwardly from the sealing material.
However, some devices such as Charge Coupled Device (CCD) have a characteristic that an active area thereof should be open, thereby it is difficult to be sealed with EMC. This is because the contact between the open active area of CCD and the EMC causes the CCD to have a defect.
Therefore, it is suggested a packaging method using a base mold and a cover for packaging the semiconductor chip such as the CCD. A conventional semiconductor package according to the method using the base mold and cover will be described accompanying with FIGS. 1 and 2.
FIG. 1 is a cross-sectional view of a conventional ceramic package using a base mold being consist of ceramic and a cover being consist of glass.
As shown in FIG. 1, a semiconductor chip (5) such as CCD is mounted on a ceramic base mold (1) and the upper part of the ceramic base mold (1) is sealed with a glass (8) in order to prevent the semiconductor chip (5) from being contaminated. The ceramic base mold (1) has a rectangular shape as a whole having a cavity (2) of step i type therein and a plurality of leads (4) are fetched/formed outwardly from a step surface (3) of one side and the other sides. The semiconductor chip (5) is attached on the bottom of a cavity (2) by using an adhesive (6) of an epoxy type. A bonding pad (5a) of the semiconductor chip (5) is electrically connected to one terminal, that is, electrode pad (4a) of the lead (4) by an aluminum or a gold wire (7).
FIG. 2 is a cross-sectional view of a conventional plastic package using EMC and glass. The same codes are used for the same parts as those of FIG. 1.
As shown in FIG. 2, a semiconductor chip (5) is adhered on a die pad (11) of a conventional lead frame (20) composed of a die pad (11), an inner lead (12), and an outer lead (13) by an adhesive (6). The bonding pad (5a) of the semiconductor chip (5) is electrically connected to the inner lead (12) of the lead frame (20) by aluminum or gold wire (7). The lower part of the semiconductor chip (5) and a selected part of the lead frame (20) are molded with EMC in order to prevent the upper part of the semiconductor chip (5) and the inner lead part which is wire-bonded thereto from being covered. The code 21 is a EMC base mold composed of EMC. The upper part of the EMC base mold (21) is sealed with a glass (8) in order to prevent the semiconductor chip (5) from being contaminated.
However, it is difficult to minimize and lighten the above-mentioned packages because of the structural characteristics thereof. And, it is also difficult to be applied to packaging of highly integrated device since there is a limitation on the number of applicable leads.
And, ceramic package is very expensive, thereby difficult to use. Moreover, a micro-gab between EMC and glass, that is, a difference in characteristics between EMC, an organic matter and glass, an inorganic matter degrades a quality and reliability of the plastic package. Contamination of the semiconductor chip due to alpha i particle from the EMC is also a cause to degrade a quality i and reliability.
Therefore, the present invention was a proposal in order to solve the problem, it is an object of the present invention to provide a semiconductor package which is minimized and thinned while having reliability and the method of fabricating the same.
According to one embodiment of the present invention, a semiconductor chip having bonding pads respectively arranged in a line adjacent to four sides of the upper surface; gold bumps formed on each bonding pad; a glass substrate which is made by forming metal patterns corresponding to the bonding pads on one side, the metal pattern consists of an inner pattern electrically connected to the bonding pad of the semiconductor chip through the gold bump, an outer pattern separated from the inner pattern and connecting pattern between the inner pattern and the outer pattern, and then forming Dam in a frame-shape on the connecting pattern and on the one side to surround the inner patterns; sealing material sealing the space between the glass substrate around the semiconductor chip to the Dam except for the outer pattern of the metal pattern; and solder balls attached on the outer patterns of each metal pattern.
According to another embodiment of the present invention, a method of fabricating a semiconductor package comprises the steps of preparing a semiconductor chip having bonding pads arranged in a line adjacent to four sides of the upper surface and glass substrate which has formed metal patterns consisting of an inner pattern, an outer pattern and a connecting pattern on the position corresponding to the bonding pads; forming gold bumps on each bonding pad; forming a Dam in a frame-shape surrounding the inner patterns on the connecting patterns and the one side of the glass substrate; bonding the semiconductor chip and the glass substrate by using the gold bump to electrically connect the bonding pad and the inner pattern; sealing a space between the glass substrate around the semiconductor chip to the Dam except for the outer pattern; and attaching solder balls on the outer patterns of each metal pattern.